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2005 Microchip Technology Inc.
Preliminary
DS41265A-page 143
PIC16F946
FIGURE 11-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 11-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 11-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
bit 1
bit 0
bit 8
bit 0
Stop
bit
Start
bit
bit 8
Stop
bit
RC7/RX/DT/
Load RSR
Read
RCIF
Word 1
RCREG
bit 8 = 0, Data Byte
bit 8 = 1, Address Byte
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
SDI/SDA/SEG8
Start
bit
bit 1
bit 0
bit 8
bit 0
Stop
bit
Start
bit
bit 8
Stop
bit
Load RSR
Read
RCIF
Word 1
RCREG
bit 8 = 1, Address Byte
bit 8 = 0, Data Byte
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
RC7/RX/DT/
SDI/SDA/SEG8
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0Ch
PIR1
EEIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN ADDEN
FERR
OERR
RX9D
0000 000x
1Ah
RCREG
USART Receive Data Register
0000 0000
8Ch
PIE1
EEIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
Legend:
x
= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
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